Gigabit Ethernet Switch 24 Port FE + 2 Port
- Provides 24 SS-SMII, 2 RGMII, 2 1000Base-X SERDES and one MII
- Built-in 2.75Mb RAM
- Support packet length up to 1536 Bytes
- Store & forward, share memory, non-blocking architecture
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Supports flow control
- 802.3x in full duplex
- Collision/carrier sense based backpressure in half duplex
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Provides up to 4K MAC address entries
- CRC/ direct hashing algorithm
- Programmable aging timer (55s~15.7hr) error < 4 %
- Configurable MAC address table
- Optional MAC address learning
- Supports porting mirroring function (Tx, Rx, Tx&Rx)
- Supports IGMP snooping function Version 1 and Version 2
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Supports flexible 3 trunking groups (Port 0 ~ port 3, port 4~ port 7, Gigabit port 1 ~ port 2)
- Load balance based on (physical port, destination MAC Address, Source MAC Address, Destination MAC Address/Source MAC Address)
- Link failure recovery
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Supports VLAN
- Port-based VLAN
- Tag-based VLAN
- Add/ remove/ modify tag based on VID or physical port
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Support Class of Service
- Port-based CoS
- 802.1Q priority tag based
- IP TOS/DSCP based (IPv4/IPv6)
- TCP/UDP port based
- 2 level of priority per port
- WRR/ First-Come-First-serve/ Strict priority
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Broadcast storm control support
- Broadcast rate control per port
- Block broadcast packet that does not belong to ARP or IP packet forwarded to CPU port
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Supports port security
- MAC address based
- IP address based
- TCP/UDP port based
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Supports Bandwidth control with/without flow control
- 480 configurable levels for p0~p23 and MII port (from 32kbps to 63.75 Mbps)
- 508 configurable levels for RGMII port (from 32kbps to 510 Mbps)
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Supports 5 port state for Spanning Tree protocol
- Blocking/ listening/ learning/ forwarding/ disabled
- Forward BPDU to CPU port
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Captures the specific packet and forward it to CPU port
- BPDU, LACP, 802.1x, GMRP, GVRP, ARP ICMP, IGMP, TCP, UDP, OSPF
- Packets with specific TCP/UDP port number
- PHY address setting for CPU, Giga 1 and Giga2 port
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Status counters for each port
- RX/TX packet count
- CRC error packet count
- Dropped packet count
- Collision count
- Programmable serial driving LED functions
- Only one 25MHz crystal is needed
- Optional 25Mhz, 50Mhz clock output
- Adjustable IO voltage (3.3/2.5v MII, 3.3/1.8v SS-SMII, 2.7V~1.9V RGMII)
- Built-in 2.5v and 1.9 regulator
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Packaging and Operating Temperature
- 144 pin EPAD. Lead-free package, 0°C~70°C
