• Single 3.3-volt operations:
− 3.3-volt read
− 3.3-volt erase
− 3.3-volt program
• Fast Program operation:
− Byte-by-Byte programming: 35 µS (typ.)
• Fast erase operation:
− Chip erase 100 mS (max.)
− Sector erase 25 mS (max.)
− Page erase 25 mS (max.)
• Fast Read access time: Tkq 11 nS
• Endurance: 10K cycles (typ.)
• Twenty-year data retention
• 8 Even sectors with 64K bytes each, which is composed of 16 flexible pages with 4K bytes
• Any individual sector or page can be erased
• Hardware protection:
− Optional 16K byte or 64K byte Top Boot Block with lockout protection
− #TBL & #WP support the whole chip hardware protection
• Flexible 4K-page size can be used as Parameter Blocks
• Low power consumption
− Active current: 12.5 mA (typ. for FWH mode)
• Automatic program and erase timing with internal VPP generation
• End of program or erase detection
− Toggle bit
− Data polling
• Latched address and data
• TTL compatible I/O
• Available packages: 32L PLCC, 32L STSOP, 40L TSOP (10 x 20 mm)
